This invention is in the field of semiconductor integrated circuits. Embodiments of this invention are more specifically directed to reliability screening of non-volatile storage elements in such integrated circuits.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example placing capacitors above the transistor level, between overlying levels of metal conductors.
FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the different capacitance exhibited by a ferroelectric capacitor in its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. In the context of a ferroelectric capacitor, the change in polarization state that occurs upon application of a polarizing voltage is reflected in charge storage. For example, referring to FIG. 1, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), by way of which polarization charge involved in the change of polarization state is retained within the capacitor as the voltage exceeds its coercive voltage Vα; on the other hand, a capacitor already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned prior to the application of the voltage. In each case, the ferroelectric capacitor also has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material). As will be evident from the following description, a stored logic state is read by interrogating the capacitance of ferroelectric capacitors to discern its polarized state.
Ferroelectric technology is now utilized in on-volatile solid-state read/write memory devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FeRAM memories are especially attractive in implantable medical devices, such as pacemakers and defibrillators.
FIG. 2a illustrates one example of a conventional FeRAM memory cell, as described in Miwa et al., “A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM”, Digest of Technical Papers: Symposium on VLSI Circuits, Paper 12-4 (IEEE, 2001), pp. 129-132, incorporated herein by reference. Cell 10 is constructed essentially in the form of a typical CMOS static RAM (SRAM) cell, with cross-coupled inverters forming a latch. In this example, one inverter is formed of p-channel transistor 2P and n-channel transistor 2N with their source-drain paths connected in series between power supply node PWR (which, in normal operation, provides the power supply voltage Vdd) and ground, and the other inverter is formed of p-channel transistor 3P and n-channel 3N, with their source-drain paths also connected in series between power supply node PWR and ground. These inverters are cross-coupled by storage node S1 at the drains of transistors 2P, 2N being connected to the gates of transistors 3P, 3N, and storage node S2 at the drains of transistors 3P, 3N being connected to the gates of transistors 2P, 2N. N-channel MOS pass transistor 4A has its source-drain path connected between storage node S1 and bit line BL, and its gate connected to word line WL; similarly, n-channel MOS pass transistor 4B has its source-drain path connected between storage node S2 and bit line BLB, and its gate also connected to word line WL. In a write operation, the complementary logic levels at storage nodes S1, L2 are written from a differential signal at bit lines BL, BLB upon word line WL turning on pass gates 4A, 4B; conversely, the state of storage nodes S1, L2 can be read by energizing word line WL and sensing the differential signal on bit line pair BL, BLB. The states at storage nodes S1, L2 remain latched while cell 10 is powered-up.
Ferroelectric capacitors 5A, 5B in cell 10 provide its non-volatile capability. In this example, capacitor 5A is connected between storage node S1 and plate line PL, and capacitor 5B is connected between storage node S2 and plate line PL. Once the state of cell 10 is present at storage nodes S1, L2, plate line PL remains at an intermediate level (e.g., Vdd/2) for both read and write operations, whether cell 10 is selected or not, so long as cell 10 is powered up. In this conventional case, capacitors 5A, 5B can be programmed to store a current state at storage nodes S1, L2 by driving plate line PL to a high voltage (e.g., power supply voltage Vdd) and then to a low voltage (e.g., ground). For example, if storage node S1 is at a high level and storage node S2 is at a low level, the high voltage level on plate line PL (greater than coercive voltage +Vα, considering plate line PL relative to storage node S2) will polarize capacitor 5B to a “+1” state (as shown in FIG. 1); capacitor 5A does not polarize at this point. Conversely, the low voltage level on plate line PL (more negative than coercive voltage −Vβ, considering plate line PL relative to storage node S1) will polarize capacitor 5A to a “−1” state; the polarization of capacitor 5B is not affected. These polarization states will remain on capacitors 5A, 5B, even after cell 10 is powered-down.
To recall the state of cell 10 as retained at capacitors 5A, 5B, plate line PL is held at a low voltage (e.g., ground) while cell 10 is powered up. Referring to FIG. 1, the powering-up of cell 10 effectively moves the applied voltage in the negative direction from the “0” voltage axis. As the voltage at power supply node PWR increases toward Vdd, the voltage across capacitors 5A, 5B crosses coercive voltage −Vβ, and capacitor 5B begins polarizing. The change in polarization of capacitor 5B causes its effective capacitance to be greater than that of capacitor 5A. This causes storage node S1 to rise toward power supply voltage Vdd faster than does storage node S2; the latch action of cell 10 will then drive storage nodes S1, S2 to their previous state, setting the state of the latch. The polarization state of capacitor 5B is destroyed in this recall (or “restore”) operation; this recall is thus a generally destructive read.
FIG. 2b illustrates another example of a conventional FeRAM cell 10′, as described in Masui et al., “Design and Applications of Ferroelectric Nonvolatile SRAM and Flip-Flop with Unlimited Read/Program Cycles and Stable Recall”, Proceedings of the Custom Integrated Circuits Conference, Paper 16-6-1(IEEE, 2003), pp. 403-406; and in Masui et al., “A Ferroelectric Memory-Based Secure Dynamically Programmable Gate Array”, J. Solid State Circuits, Vol. 38, No. 5 (IEEE, May 2003), pp. 715-725; both incorporated herein by reference. Cell 10′ of FIG. 2b is similarly constructed as cell 10 of FIG. 2a, with the same reference numerals used for similar elements, but includes two additional ferroelectric capacitors 7A, 7B. Capacitor 7A is connected between storage node S1 and plate line PL2, and capacitor 7B is connected between storage node S2 and plate line PL2; plate line PL1 refers to the plate line connected to capacitors 5A, 5B in this FIG. 2b. Capacitors 7A, 7B are much larger capacitors than their capacitors 5A, 5B, for example having three times the dielectric area and thus three times the linear capacitance. The operation of cell 10′ in its read and write operations is essentially the same as that of cell 10 of FIG. 2a, however both plate lines PL1, PL2 may be maintained at ground potential in normal operation for read and write cycles of cell 10′ as an SRAM cell. Programming of ferroelectric capacitors 5A, 5B, 7A, 7B in cell 10′ is accomplished in similar fashion as described above. In this case, both plate lines PL1, PL2 are driven to a high voltage (e.g., Vdd) and then to a low voltage (e.g., ground) while cell 10′ remains powered up. The logic level at storage node S1 determines the polarization of capacitors 5A, 7A, while the logic level at storage node S2 determines the polarization of capacitors 5B, 7B.
Plate lines PL1, PL2 receive separate voltages during the recall operation in this cell 10′. Recall begins with plate lines PL1, PL2 at a low voltage (e.g., ground), while pass transistors 4A, 4B are held off by word line WL at an inactive low level. Plate line PL1 is then driven to a high voltage (e.g., Vdd) while plate line PL2 remains at a low voltage, at which point cell 10′ is powered up. With plate line PL1 at Vdd and plate line PL2 at ground, the voltages at storage nodes S1, S2 are based on a voltage divider of the capacitances of ferroelectric capacitors 5A, 5B, 7A, 7B, which depends on their differing polarization states.
For example, if storage node S1 is at a high logic level and storage node S2 at a low logic level, programming of ferroelectric capacitors 5A, 5B, 7A, 7B will result in ferroelectric capacitors 5A, 7A polarized to the “−1” state, and ferroelectric capacitors 5B, 7B polarized to the “+1” state. In the recall operation, with plate line PL1 at Vdd and plate line PL2 at ground, the voltage divider of ferroelectric capacitors 5A, 5B, 7A, 7B at each of storage nodes S1, S2 operates as:
    =            V      dd        ⁡          (                                        +                      C            7                              )      where VS is the voltage at one of storage nodes S1, S2, C5 is the capacitance of its associated ferroelectric capacitor 5, and C7 is the capacitance of its associated ferroelectric capacitor 7 (C7>C5 in this example, as described above). In this case, ferroelectric capacitor 5A at storage node S1 has a higher capacitance because of its “−1” polarization state than will ferroelectric capacitor 5B in its “+1” state. Accordingly, the voltage VS1 at storage node S1 will be higher than the voltage VS2 at storage node S2, by virtue of the higher effective capacitance of capacitor 5A than that of capacitor 5B. One can also consider this effect as storage node S1 being charged by the polarization charge from capacitor 5A as changes its polarization state; storage node S2 does not receive this polarization charge, because capacitor 5B is not changing state. As a result, as cell 10′ is powered-up, the differential voltage at storage nodes S1, S2 established by ferroelectric capacitors 5A, 5B, 7A, 7B is latched into the cross-coupled inverters of cell 10′, with storage node S1 latched high and storage node S2 latched low in this example. As before, this restore operation is destructive of the programmed state, requiring reprogramming of capacitors 5A, 5B, 7A, 7B when appropriate.
Ferroelectric capacitors are now also implemented in logic circuits, for example to store the state of latch nodes upon power-down, so that this previous state can be restored on power-up. Another use of ferroelectric capacitors in logic circuits is to provide non-volatile storage of configuration information, so that power-up of the logic circuit will immediately load that stored configuration information into various latch nodes within the logic circuit. These and other uses of non-volatile elements such as ferroelectric capacitors in logic circuits are becoming popular.
FIG. 2c illustrates an example of conventional ferroelectric flip-flop 16, as used in the data or control flow of a large-scale logic circuit, and in which ferroelectric capacitors 15A, 15B, 17A, 17B operate to store the state of flip-flop 16 on power-down, and to restore that logic state as it is again powered-up. The construction and operation of an example of a flip-flop such as that shown in FIG. 2c is described in Masui et al., “Design and Applications of Ferroelectric Nonvolatile SRAM and Flip-Flop with Unlimited Read/Program Cycles and Stable Recall”, Proceedings of the Custom Integrated Circuits Conference, Paper 16-6-1(IEEE, 2003), pp. 403-406, incorporated herein by reference. In the simplified example of FIG. 2c, input data line D is received at pass gate 9A, which connects input data line D to storage node S1 according to the level of clock signal CLK. Pass gate 9B selectively connects the output of inverter 8B to storage node S1. Pass gates 9A, 9B are each CMOS pass gates, constructed as a p-channel MOS transistor in parallel with an n-channel MOS transistor, with the gates of the two transistors receiving complementary versions of clock signal CLK (i.e., clock signal CLK itself and via inverter 11). In this example, pass gates 9A, 9B are complementary with one another, such that one is turned on when the other is turned off, and vice versa.
Inverter 8B is one of a pair of cross-coupled inverters providing the latch function in flip-flop 16, and receives storage node S2 at its input. The other inverter 8A in the cross-coupled pair has its input coupled to storage node S1, and drives storage node S2, completing the cross-coupling. In this case, the output of flip-flop 16 is taken on output data line Q from storage node S2, via inverter 14 (so that the output data level corresponds to that of input data line D). Bias to inverters 8A, 8B is provided from power supply node PWR by p-channel MOS transistor 13A and from ground by re-channel MOS transistor 13B. The gates of transistors 13A, 13B are driven by enable signal EN (inverted by inverter 19 in the case of transistor 13A).
Ferroelectric capacitors 15A, 15B, 17A, 17B in conventional flip-flop 16 provide the non-volatile retention of its state upon its power-down (e.g., enable signal EN driven inactive low). Similarly as in memory cell 10′ of FIG. 2b, ferroelectric capacitors 15A, 17A are connected between storage node S1 and plate lines PL1, PL2, respectively; similarly, ferroelectric capacitors 15B, 17BA are connected between storage node S2 and plate lines PL1, PL2, respectively. Ferroelectric capacitors 17A, 17B are typically larger than ferroelectric capacitors 15A, 15B, and provide the voltage divider load for the recall or restore operation, as described above in connection with FIG. 2b. The operation of flip-flop 16 in programming its ferroelectric capacitors 15A, 15B, 17A, 17B with the current state of flip-flop 16 (i.e., storage nodes 51, S2), and in restoring that state on power-up, follows that described above relative to FIG. 2b. 
Circuits such as memory cells 10, 10′, and flip-flop 16, provide important non-volatile functionality in many modern integrated circuits. Non-volatile retention of memory contents, and logic states, as provided by these circuits enable the use of high-performance integrated circuit functionality in many applications previously thought to be impractical in the absence of non-volatile storage capability. However, ferroelectric elements such as capacitors are known to be vulnerable to later-life degradation due to various effects. Repeated read/write cycles (i.e., polarization and destructive read operations) can degrade the polarizability of ferroelectric capacitors, as can the effects of time and temperature.
For example, the mechanism of “imprint” is a well-known “end-of-life” mechanism that has been observed in ferroelectric devices. Imprint is exhibited by permanent shifts in the shape of the Q-V characteristic loop, generally appearing as flattened slopes in the transition curves and shifting in the polarization charge levels that result in an overall loss of area within the hysteresis loop. One type of imprint, referred to as “dynamic” imprint, results from repetitive or extended application of voltage exceeding one of the coercive voltages Vα or Vβ, as the case may be, which effectively rewrites the same data in the cell. Imprint of the static type refers to permanent shifts in the polarization characteristic due to the capacitor remaining in one polarization state over time without external bias. FIG. 3 illustrates the effect of imprint on the Q-V characteristic of an example of a ferroelectric capacitor, by way of shifted characteristic curve 20 relative to its initial characteristic curve 22. In this somewhat extreme case, the effects of imprint include inadequate polarization of the capacitor in either state, as well as poorly defined coercive voltages.
As evident from FIG. 3, severe imprint greatly reduces the ability to distinguish the two polarization states from one another. In the context of memory cells 10, 10′ and flip-flop 16 described above, in which the polarization states restore the previous circuit state according to capacitance differences between the polarization states, one can see that the capacitances C(−1), C(+1) indicated by the slopes of the Q/V transitions for the two polarization states from zero applied volts to a positive voltage are much closer to one another after the effects of imprint have set in (curve 20), than at time-zero (curve 22). Because the restore or recall operation relies on differences in capacitance between the two states, this weakness in polarization increases the likelihood that device imbalances, or noise events, can cause the memory cell or logic element incorporating ferroelectric capacitors to fall victim to a data error on restoring a programmed state. Certainly the likelihood of such errors increases as degradation of the ferroelectric material over time, temperature, and usage occurs. Such data errors have been observed in modern high-performance integrated circuits incorporating ferroelectric capacitors for non-volatile data and logic state retention.
It has been observed that any sizable population of ferroelectric capacitors will exhibit a distribution of polarization characteristics, and thus will include some ferroelectric capacitors that are “weaker” than others upon manufacture, in regard to the ability to electrically distinguish between their polarization states. Under the reasonable assumption that degradation of the polarization capability over time, temperature, and usage is uniform across the population of elements, those capacitors exhibiting the weaker polarization characteristic at time-zero will be the first to cause circuit failure in use. It would therefore be useful to perform a time-zero (i.e., at wafer level, or after packaging, or both) electrical test to screen out, from a population of manufactured integrated circuits, those devices that will be the earliest to fail within a particular threshold time.
Of course, in circuit implementations such as memory cells and logic circuits, it is difficult if not impossible to obtain a direct measurement of the polarization characteristics of each embedded ferroelectric capacitor. Rather, the polarization behavior of these elements can only be interrogated in an indirect manner. In the case of memory cells such as those described above in connection with FIGS. 2a and 2b, one conventional screening approach is to reduce the power supply (Vdd) bias applied to the memory cells 10, 10′ when performing a restore operation. This reduced power supply bias will be reflected in weaker distinction in the voltages presented by the ferroelectric capacitors to the storage nodes during the restore operation. However, it has been observed that there is a poor correlation between those devices failing such a reduced Vdd storage test, and those devices that exhibit the weakest reliability due to time-dependent polarization degradation, especially as reliability requirements continue to become more stringent.
Another conventional approach to time-zero screening of non-volatile latches in memory cells is to apply a small disturb differential voltage from the bit lines to the storage nodes, prior to performing a restore or recall operation. That approach is somewhat cumbersome insofar as construction of write circuits in the memories is concerned. In addition, this bit line disturb voltage approach is not applicable to logic circuits such as flip-flop 16 that do not have accessible “bit lines” at all, especially for such circuits that are embedded in complex logic chains and data paths.
By way of further background, copending and commonly assigned U.S. patent application Ser. No. 12/142,568, published as U.S. Patent Application Publication No. US 2009/0316469 A1, incorporated herein by reference, describes a test procedure for screening weak ferroelectric capacitors in a non-volatile memory, using a short high temperature bake.